Testing for judging whether semiconductor devices (for example, LSI: Large Scale Integration) are operating correctly is an indispensable technology at the product shipment stage and in fabrication stages such as fault analysis.
As one typical test of this type, a low-speed test method has been used for detecting “stuck-at faults” in which a signal degenerates to “0” or “1” due to a short fault or due to an open fault of a signal line.
However, the increased operating speed of LSI that has accompanied the miniaturization of LSI in recent years has led to an increase in delay faults that cannot be detected by a low-speed test method. A delay fault is a fault in which a signal change is not passed between flip-flops (hereinbelow abbreviated as “FF”) within a prescribed time interval.
When testing LSI, a test pattern is typically applied as input from the outside and analysis is then carried out regarding whether the LSI output signal matches an expected value.
The simplest method of observing the state of an LSI is a method of supplying the signal of a node that is to be observed to the chip exterior by way of an external output pin of the LSI. However, the number of external output pins of an LSI is typically less than the number of all internal nodes, and it is therefore impossible to extract the signals of all internal nodes to the outside by way of the external output pins of the LSI.
A scanning method is therefore considered as a method of raising observation capabilities.
In a scanning method, the FFs in a circuit are replaced by scan flip-flops (hereinbelow abbreviated as “scan FF”) and the scan FFs are connected in series.
A scan FF includes a data input terminal that accepts a signal from the logic circuit that is the test-object, a scan-in terminal that accepts the test pattern, a mode terminal that accepts a mode signal, a clock terminal, and an output terminal, and further includes a test mode and a normal mode. The test pattern is made up from an initial value that is set to each scan FF.
When the mode signal indicates the test mode, each of the scan FFs that are connected in series: operates as a shift register; accepts input from, of the data input terminal and scan-in terminal, the scan-in terminal; and sets (scans in) the state of the circuit interior (its own circuit interior) based on the instructions applied as input to the scan-in terminal (an initial value among the test pattern that corresponds to itself). In addition, in the test mode, the scan FF supplies (scans out) to the outside the state of the circuit interior (its own circuit interior).
When the mode signal indicates the normal mode, the scan FF accepts, from among the data input terminal and the scan-in terminal, input (the signal from the logic circuit that is the test-object) from the data input terminal, and operates as a normal FF to implement testing of the logic circuit.
In a delay test, analysis is carried out between two FFs in a circuit to determine if the circuit operation brought about by a signal supplied from one of the FFs is latched within a prescribed time interval by the other FF. The scan method is also effective in a delay test as a method of setting the initial value of the FFs in a circuit and observing the test results. The scan method is widely used for this reason.
In a delay test that uses the scan method, a scan FF is first operated in the test mode, and the state of the scan FF is set to any (specifically, an initial value included in the test pattern) based on the test pattern from the scan-in terminal. At this time, the output of the scan FF is the initial value.
The scan FF is next set to the normal mode, whereby the input from the data input terminal comes into effect. A scan FF in the normal mode carries out normal operations at a particular test frequency and carries out the operation test of a logic circuit in the interval of exactly two clocks. At this time, a signal transition is brought about by the first clock in the scan FF and this signal transition is applied as input to the logic circuit. The operation result of the logic circuit is latched in the scan FF at the next clock.
The scan FF is next set to the test mode again. Each scan FF in the test mode operates as a shift register, and the latched results are supplied to the chip exterior in accordance with the input of a clock. Determining whether the results are correct is carried out based on this output result.
The above-described test operation is repeatedly carried out at different test operating frequencies using the same test pattern, and delay faults are detected by determining whether the results are correct.
In Patent Documents 1-5, a technology is disclosed in which a new function is added to scan FFs to carry out efficient testing.
In Patent Document 1 and Patent Document 2, a technology is disclosed in which a scan FF is considered as two latches, and by further adding a latch, a plurality of values are held in the scan FFs. The activation of test paths in the delay test is thus facilitated.
In Patent Document 3 and Patent Document 4, a technology is disclosed in which an FF is newly added to a scan FF and a new value thus held. In this way, the direct supply of a particular FF value to the outside eliminates the need for scan-out, or the scan-out of the arithmetic results of the FF is realized by using a comparative function.
Patent Document 5 discloses a method that compresses test results by a logical circuit to identify a fault location.
Patent Document 1: JP-A-2007-187458
Patent Document 2: JP-A-2002-124852
Patent Document 3: JP-A-H05-060835
Patent Document 4: JP-A-H10-339762
Patent Document 5: JP-A-2004-361351